Girg T, Beck C, Dietz M, Hagelauer AM, Kissinger D, Weigel R (2016)
Publication Type: Conference contribution, Conference Contribution
Publication year: 2016
Publisher: IEEE
Pages Range: 1-4
Conference Proceedings Title: 2016 IEEE 14th International NEWCAS Conference
Event location: Vancouver
DOI: 10.1109/NEWCAS.2016.7604745
An integrated analog frequency multiplier for a novel high data rate communication system has been developed to multiply a 18 GHz input signal by ten to generate a 180 GHz output signal. With a first step the 18 GHz input signal is fed into a times five edge combiner, which generates an intermediate frequency of 90 GHz. Therefore five different phases with a delta of 72 degree are needed, that are provided by an active allpass filter chain. In a second step the 90 GHz intermediate frequency is given into a double-balanced Gilbert cell mixer. Here, frequency doubling is achieved by feeding the same signal into the LO and RF port of the mixer. Hence, the overall output frequency of 180 GHz results in 180 GHz with a simulated output power of -7 dBm. All simulations are done post-layout. The chip is implemented in a 130 nm BiCMOS technology with a chip area of 0.9 mm x 1 mm.
APA:
Girg, T., Beck, C., Dietz, M., Hagelauer, A.M., Kissinger, D., & Weigel, R. (2016). A 180 GHz Frequency Multiplier in a 130 nm SiGe BiCMOS Technology. In 2016 IEEE 14th International NEWCAS Conference (pp. 1-4). Vancouver: IEEE.
MLA:
Girg, Thomas, et al. "A 180 GHz Frequency Multiplier in a 130 nm SiGe BiCMOS Technology." Proceedings of the 2016 IEEE 14th International NEWCAS Conference, Vancouver IEEE, 2016. 1-4.
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