Franchi N, Weigel R, Cai Z, Schmid J, Rauch H (2011)
Publication Type: Conference contribution
Publication year: 2011
Conference Proceedings Title: 23. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen
Event location: Passau, Germany
Obsolescence of electronic components is a serious problem and challenge for electronics industry affecting nearly every electronic system. The problem of ensuring backward compatibility caused by replacing obsolete system parts must be solved by reproducing the specific functionality and system behaviour of the replaced component. This paper addresses an online configurable I/O architecture that allows user-defined I/O signal manipulations via JTAG interface for FPGA logic designs with integrated IP soft core as replacement for an obsolete chip. In addition to this the flexible configuration affords the opportunity to realize an automated test strategy. Thus embedded-core based system chips can be analyzed, tested and re-/configured automatically.
APA:
Franchi, N., Weigel, R., Cai, Z., Schmid, J., & Rauch, H. (2011). A new IP core integration concept for signal manipulation and timing adjustment using a configurable I/O architecture. In 23. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen. Passau, Germany.
MLA:
Franchi, Norman, et al. "A new IP core integration concept for signal manipulation and timing adjustment using a configurable I/O architecture." Proceedings of the 23. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Passau, Germany 2011.
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