A Generic VHDL Template for 2D Stencil Code Applications on FPGAs
Schmidt M, Reichenbach M, Fey D (2012)
Publication Type: Conference contribution
Publication year: 2012
Edited Volumes: Proceedings - 2012 15th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, ISORCW 2012
Pages Range: 180 -187
Conference Proceedings Title: Proceedings of the 15th IEEE International Symposium of Object/Component/Service-Oriented Real-Time Distributed Computing Workshops (ISORCW)
Event location: Shenzen, China
Abstract
The efficient realization of self-organizing systems based on 2D stencil code applications, like our developed Marching Pixel algorithms, is a great challenge. They are data-intensive and also computational-intensive, because often a high number of iterations is required. FPGAs are predestined for the realization of these algorithms. They are very flexible, allow a scalable parallel processing and have a moderate power consumption, even in high-performance versions. Therefore, FPGAs are highly qualified to make these applications also real-time capable. Our goal was to implement an efficient parameterizable buffering and parallel processing scheme for such operations in FPGAs, to process them as fast as possible. We developed a generic VHDL template which allows a scalable parallelization and pipelining of 2D stencil code applications in relation to application and hardware constraints. © 2012 IEEE.
Authors with CRIS profile
Michael Schmidt
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Marc Reichenbach
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Dietmar Fey
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
How to cite
APA:
Schmidt, M., Reichenbach, M., & Fey, D. (2012). A Generic VHDL Template for 2D Stencil Code Applications on FPGAs. In Proceedings of the 15th IEEE International Symposium of Object/Component/Service-Oriented Real-Time Distributed Computing Workshops (ISORCW) (pp. 180 -187). Shenzen, China, CN.
MLA:
Schmidt, Michael, Marc Reichenbach, and Dietmar Fey. "A Generic VHDL Template for 2D Stencil Code Applications on FPGAs." Proceedings of the Workshop of Self-Organizing Real-Time Systems (SORT), Shenzen, China 2012. 180 -187.
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