A Combination of a Digital Foreground and Background Calibration for a 16Bit and 200MS/s Pipeline Analog-to-Digital Converter

Löhr R, Stadelmayer M, Röber J, Ohnhäuser F, Weigel R (2017)

Publication Language: English

Publication Status: Published

Publication Type: Conference contribution

Future Publication Type: Article in Edited Volumes

Publication year: 2017

Publisher: IEEE

Event location: Italien

Abstract

High-Performance Analog-to-Digital Converter

(ADC) have high requirements concerning sampling rate and

linearity. Therefore a new formula is derived to determine,

which pipeline stage dependent on the used capacitor sizes

needs to be calibrated for the targeted linearity. Furthermore,

a model of a 16 bit and 200MS/s pipeline ADC is described. A

combination of a digital foreground and a digital background

calibration is presented, which can compensate linear errors

and achieves a DNL smaller than ±1 and a THD of -88 dB.

Authors with CRIS profile

Robert Löhr Lehrstuhl für Technische Elektronik (LTE) Robert Weigel Lehrstuhl für Technische Elektronik (LTE)

How to cite

APA:

Löhr, R., Stadelmayer, M., Röber, J., Ohnhäuser, F., & Weigel, R. (2017). A Combination of a Digital Foreground and Background Calibration for a 16Bit and 200MS/s Pipeline Analog-to-Digital Converter. In Proceedings of the ECCTD. Italien: IEEE.

MLA:

Löhr, Robert, et al. "A Combination of a Digital Foreground and Background Calibration for a 16Bit and 200MS/s Pipeline Analog-to-Digital Converter." Proceedings of the ECCTD, Italien IEEE, 2017.

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