Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-Core Processor

Salcic Z, Nadeem M, Park H, Teich J (2016)

Publication Type: Conference contribution

Publication year: 2016

Pages Range: 233-240

Conference Proceedings Title: Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16)

Event location: Lyon FR

Authors with CRIS profile

Heejong Park Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Involved external institutions

University of Auckland NZ New Zealand (NZ)

How to cite

APA:

Salcic, Z., Nadeem, M., Park, H., & Teich, J. (2016). Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-Core Processor. In Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16) (pp. 233-240). Lyon, FR.

MLA:

Salcic, Zoran, et al. "Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-Core Processor." Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16), Lyon 2016. 233-240.

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