Prof. Dr. Joachim Neves Rodrigues

Lehrstuhl für System-on-Chip

A 65 nm single stage 28 fJ/cycle 0.12 to 1.2V level-shifter (2014) Mohammadi B, Rodrigues JN Conference contribution Next generation digital front-end for multi-standard concurrent reception (2013) Diaz I, Zhang C, Hollevoet L, Svensson J, Rodrigues JN, Wilhclmsson L, Olssson T, et al. Conference contribution An ultra-low-power application-specific processor with sub-VT memories for compressed sensing (2013) Constantin J, Dogan A, Andersson O, Meinerzhagen P, Rodrigues JN, Atienza D, Burg A Conference contribution A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs (2013) Muller C, Malkowsky S, Andersson O, Mohammadi B, Sparso J, Rodrigues JN Conference contribution Ultra low energy design exploration of digital decimation filters in 65 nm dual-VT CMOS in the sub-VT domain (2013) Yasser Sherazi SM, Rodrigues JN, Akgun OC, Sjöland H, Nilsson P Journal article Approximative matrix inverse computations for very-large MIMO and applications to linear pre-coding systems (2013) Prabhu H, Rodrigues JN, Edfors O, Rusek F Conference contribution FPGA development approach for accelerator systems with high integration complexity (2013) Dedic J, Zagar K, Söderqvist A, Claesson N, Tavcar R, Rodrigues JN Conference contribution Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS (2013) Andersson O, Mohammadi B, Meinerzhagen P, Burg A, Rodrigues JN Conference contribution Ultra-low-power error correction circuits: Technology scaling and Sub-VT Operation (2012) Winstead C, Rodrigues JN Journal article High-level energy estimation in the Sub-V T domain: Simulation and measurement of a cardiac event detector (2012) Akgun OC, Rodrigues JN, Leblebici Y, Öwall V Journal article