Dr.-Ing. Alexandru-Petru Tanase

Sonderforschungsbereich/Transregio 89 Invasives Rechnen Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays (2016) Witterauf M, Tanase AP, Hannig F, Teich J Conference contribution Providing Fault Tolerance Through Invasive Computing (2016) Lari V, Weichslgartner A, Tanase AP, Witterauf M, Khosravi F, Teich J, Heißwolf J, et al. Journal article A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators (2016) Bhadouria VS, Tanase AP, Schmid M, Hannig F, Teich J, Ghoshal D Journal article Adaptive Fault Tolerance in Tightly Coupled Processor Arrays with Invasive Computing (2015) Witterauf M, Tanase AP, Hannig F, Teich J Conference contribution Adaptive fault tolerance through invasive computing (2015) Witterauf M, Tanase AP, Teich J, Lari V, Zwinkau A, Snelting G Conference contribution, Conference Contribution A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays (2015) Lari V, Tanase AP, Teich J, Witterauf M, Khosravi F, Hannig F, Meyer B Conference contribution, Conference Contribution Techniques for on-demand structural redundancy for massively parallel processor arrays (2015) Teich J, Lari V, Tanase AP, Witterauf M, Khosravi F, Meyer B Journal article, Original article On-demand fault-tolerant loop processing on massively parallel processor arrays (2015) Tanase AP, Witterauf M, Teich J, Hannig F, Lari V Conference contribution, Conference Contribution Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays (2015) Tanase AP, Witterauf M, Hannig F, Teich J Conference contribution, Conference Contribution Timing Analysis of a Heterogeneous Architecture with Massively Parallel Processor Arrays (2014) Gangadharan D, Tanase AP, Hannig F, Teich J Conference contribution