Dr.-Ing. Daniel Ziener

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

FPGA-based Testbed for Timing Behavior Evaluation of the Controller Area Network (CAN) (2012) Ziermann T, Butiu A, Teich J, Ziener D Conference contribution Symbolic System-level Design Methodology for Multi-Mode Reconfigurable Systems (2012) Wildermann S, Reimann F, Ziener D, Teich J Journal article System Level Synthesis Flow for Self-adaptive Multi-mode Reconfigurable Systems (2012) Wildermann S, Reimann F, Ziener D, Teich J Conference contribution On-the-fly Composition of FPGA-Based SQL Query Accelerators Using A Partially Reconfigurable Module Library (2012) Dennl C, Ziener D, Teich J Conference contribution Partial Reconfiguration on FPGAs in Practice - Tools and Applications (2012) Koch D, Torresen J, Beckhoff C, Ziener D, Dennl C, Breuer V, Teich J, et al. Conference contribution Symbolic Design Space Exploration for Multi-Mode Reconfigurable Systems (2011) Wildermann S, Reimann F, Ziener D, Teich J Conference contribution Verifying the Authorship of Embedded IP Cores: Watermarking and Core Identification Techniques (Keynote) (2011) Teich J, Ziener D Conference contribution Unifying Partitioning and Placement for SAT-based Exploration of Heterogeneous Reconfigurable SoCs (2011) Wildermann S, Ziener D, Teich J Conference contribution Runtime Stress-Aware Replica Placement on Reconfigurable Devices under Safety Constraints (2011) Angermeier J, Ziener D, Glaß M, Teich J Conference contribution An FPGA Implementation of a Threat-based Strategy for Connect6 (2011) Ziermann T, Schmidt B, Mühlenthaler M, Ziener D, Angermeier J, Teich J Conference contribution