Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Topic 18: Embedded Parallel Systems (2006) Teich J, Kaxiras S, Plaks T, Flautner K Conference contribution Searching RC5-Keys with Distributed Reconfigurable Computing (2006) Koch D, Teich J, Körber M Conference contribution Power Aware Design (2006) Streichert T Conference contribution Placing Functionality in Fault-Tolerant Hardware/Software Reconfigurable Networks (2006) Streichert T Conference contribution Mapping of Nested Loop Programs onto Massively Parallel Processor Arrays with Memory and I/O Constraints (2006) Dutta H, Hannig F, Teich J Conference contribution Identifying FPGA IP-Cores based on Lookup Table Content Analysis (2006) Ziener D, Aßmus Stefan AS, Teich J Conference contribution Hierarchical Partitioning for Piecewise Linear Algorithms (2006) Dutta H, Hannig F, Teich J Conference contribution FPGA Core Watermarking Based on Power Signature Analysis (2006) Ziener D, Teich J Conference contribution Communication-conscious Mapping of Regular Nested Loop Programs onto Massively Parallel Processor Arrays (2006) Hannig F, Merker R, Siegel S, Teich J Conference contribution Bridging the Gap between Relocation and Available Technology: The Erlangen Slot Machine (2006) Göhringer D, Majer M, Teich J Conference contribution