Scheduling of partitioned regular algorithms on processor arrays with constrained resources

Teich J, Thiele L, Zhang L (1996)


Publication Type: Conference contribution

Publication year: 1996

Publisher: IEEE

Edited Volumes: International Conference on Application-Specific Systems, Architectures and Processors, Proceedings

Pages Range: 131-144

Conference Proceedings Title: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP´96)Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP´96)Int. Conf. on Application-Specific Systems, Architectures, and Processors

Event location: Chicago, U.S.A.,

Abstract

A single integer linear programming model for optimally scheduling partitioned regular algorithms is presented. The herein presented methodology differs from existing methods in the following capabilities: 1) Not only constraints on the number of available processors and communication capabilities are taken into account, but also processor caches and constraints on the size of available memories are modeled and taken into account in the optimization model. 2) Different types of processors can be handled. 3) The size of the optimization model (number of integer variables) is independent of the size of the tiles to be executed. Hence, 4) the number of integer variables in the optimization model is greatly reduced such that problems of relevant size can be solved in practical execution time.

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APA:

Teich, J., Thiele, L., & Zhang, L. (1996). Scheduling of partitioned regular algorithms on processor arrays with constrained resources. In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP´96)Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP´96)Int. Conf. on Application-Specific Systems, Architectures, and Processors (pp. 131-144). Chicago, U.S.A.,: IEEE.

MLA:

Teich, Jürgen, Lothar Thiele, and L Zhang. "Scheduling of partitioned regular algorithms on processor arrays with constrained resources." Proceedings of the Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP´96),, Chicago, U.S.A., IEEE, 1996. 131-144.

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