Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures

Wolinski C, Kuchcinski K, Teich J, Hannig F (2008)


Publication Type: Conference contribution

Publication year: 2008

Publisher: IEEE Press

Edited Volumes: Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008

City/Town: New York

Pages Range: 345-352

Conference Proceedings Title: Proceedings of the 11th Euromicro Conference on Digital System Design

Event location: Parma IT

DOI: 10.1109/DSD.2008.1

Abstract

In this paper, we introduce a constraint programming-based approach for optimization of routing and reconfiguration overhead for a class of reconfigurable processor array architectures called weakly programmable. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for optimal routing of data between processors as well as for minimization of the routing area and the reconfiguration overhead when switching between the execution of these algorithms. In fact, applying the switching can be accomplished in just a few clock cycles. Our experiments confirm that our method can minimize routing overhead and reduce reconfiguration time significantly. © 2008 IEEE.

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APA:

Wolinski, C., Kuchcinski, K., Teich, J., & Hannig, F. (2008). Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. In Proceedings of the 11th Euromicro Conference on Digital System Design (pp. 345-352). Parma, IT: New York: IEEE Press.

MLA:

Wolinski, Christophe, et al. "Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures." Proceedings of the 11th Euromicro Conference on Digital System Design (DSD), Parma New York: IEEE Press, 2008. 345-352.

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