Scheduling and communication-aware mapping of HW-SW modules for dynamically and partially reconfigurable SoC architectures

Angermeier J, Fekete SP, Göhringer D, Majer M, Teich J, Van Der Veen JC (2007)

Publication Type: Conference contribution

Publication year: 2007

Publisher: VDE-Verlag

City/Town: Berlin

Pages Range: 151-160

Conference Proceedings Title: Proc. of the 20th International Conference on Architecture of Computing Systems

Event location: Zurich CH

Authors with CRIS profile

Josef Angermeier Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Optimization methodologies for reconfiguration management on reconfigurable hardware nodes (ReCoNodes) SPP 1148: Rekonfigurierbare Rechensysteme June 1, 2003 - May 31, 2009

Involved external institutions

Technische Universität Braunschweig DE Germany (DE)

How to cite

APA:

Angermeier, J., Fekete, S.P., Göhringer, D., Majer, M., Teich, J., & Van Der Veen, J.C. (2007). Scheduling and communication-aware mapping of HW-SW modules for dynamically and partially reconfigurable SoC architectures. In Proc. of the 20th International Conference on Architecture of Computing Systems (pp. 151-160). Zurich, CH: Berlin: VDE-Verlag.

MLA:

Angermeier, Josef, et al. "Scheduling and communication-aware mapping of HW-SW modules for dynamically and partially reconfigurable SoC architectures." Proceedings of the ARCS '07 - 20th International Conference on Architecture of Computing Systems, Zurich Berlin: VDE-Verlag, 2007. 151-160.

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