Power-efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures

Kissler D, Strawetz A, Hannig F, Teich J (2008)

Publication Type: Conference contribution

Publication year: 2008

Pages Range: 307–317

Conference Proceedings Title: Proceedings of the 18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

Event location: Lisbon PT

Authors with CRIS profile

Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Co-Design of Massively Parallel Embedded Processor Architectures (CoMap) Jan. 1, 2005 - Dec. 31, 2011

How to cite

APA:

Kissler, D., Strawetz, A., Hannig, F., & Teich, J. (2008). Power-efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. In Proceedings of the 18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) (pp. 307–317). Lisbon, PT.

MLA:

Kissler, Dmitrij, et al. "Power-efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures." Proceedings of the 18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Lisbon 2008. 307–317.

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