Teich J, Bednara M (2003)
Publication Type: Journal article
Publication year: 2003
Publisher: Springer Verlag (Germany)
Pages Range: 149-165
We consider the problem of automatic mapping of computation-intensive loop nests onto FPGA hardware. The regular cell array structure of these chips reflects the parallelism in regular loop-like computations. Furthermore, the flexibility of FPGAs allows the cost-effective implementation of reconfigurable high performance processor arrays. So far, there exists no continuous design flow that allows automated generation of FPGA configuration data from a loop nest specified in a high level language. Here, we present a methodology for automatic generation of synthesizable VHDL code specifying a processor array and optimized for FPGA implementation.
APA:
Teich, J., & Bednara, M. (2003). Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms. Journal of Supercomputing, 149-165. https://dx.doi.org/10.1023/A:1024447517501
MLA:
Teich, Jürgen, and Marcus Bednara. "Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms." Journal of Supercomputing (2003): 149-165.
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