Introducing a Performance Model for Bandwidth-Limited Loop Kernels
Eitzinger J, Hager G (2010)
Publication Type: Conference contribution
Publication year: 2010
Journal
Publisher: Springer-verlag
Edited Volumes: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Series: Lecture Notes in Computer Science
City/Town: Berlin Heidelberg
Book Volume: 6067
Pages Range: 615-624
Conference Proceedings Title: Parallel Processing and Applied Mathematics
Event location: Wroclaw, Poland
URI: http://www.springerlink.com/content/m720118145140122/
DOI: 10.1007/978-3-642-14390-8_64
Abstract
We present a diagnostic performance model for bandwidth-limited loop kernels which is founded on the analysis of modern cache based microarchitectures. This model allows an accurate performance prediction and evaluation for existing instruction codes. It provides an in-depth understanding of how performance for different memory hierarchy levels is made up. The performance of raw memory load, store and copy operations and a stream vector triad are analyzed and benchmarked on three modern x86-type quad-core architectures in order to demonstrate the capabilities of the model. © 2010 Springer-Verlag Berlin Heidelberg.
Authors with CRIS profile
Jan Eitzinger
Regionales Rechenzentrum Erlangen (RRZE)
Georg Hager
Regionales Rechenzentrum Erlangen (RRZE)
How to cite
APA:
Eitzinger, J., & Hager, G. (2010). Introducing a Performance Model for Bandwidth-Limited Loop Kernels. In Parallel Processing and Applied Mathematics (pp. 615-624). Wroclaw, Poland, PL: Berlin Heidelberg: Springer-verlag.
MLA:
Eitzinger, Jan, and Georg Hager. "Introducing a Performance Model for Bandwidth-Limited Loop Kernels." Proceedings of the 8th International Conference, PPAM 2009 , Revised Selected Papers, Part I, Wroclaw, Poland Berlin Heidelberg: Springer-verlag, 2010. 615-624.
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