Output Serialization for FPGA-based and Coarse-grained Processor Arrays

Hannig F, Teich J (2005)

Publication Type: Conference contribution

Publication year: 2005

Edited Volumes: Proceedings of the 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'05

Pages Range: 78-84

Conference Proceedings Title: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms

Event location: Las Vegas, NV US

ISBN: 1-932415-74-2

Abstract

This paper deals with the mapping of loop programs onto processor arrays either implemented in an FPGA or available as (reconfigurable) coarse-grained processor architectures. Usually the proportion of processing elements to I/O-interfaces is much higher whereby problems of data transportation and synchronization are arising. In this realm, we propose a systematic approach in order to feed-out data. Here, (a) an efficient routing strategy is presented and (b) a novel retiming strategy is given in order to ensure collision free output serialization.

Authors with CRIS profile

Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Co-Design of Massively Parallel Embedded Processor Architectures (CoMap) Jan. 1, 2005 - Dec. 31, 2011 Dedizierte massiv parallele Systeme (PARO) Jan. 3, 2000 - Jan. 3, 2003

How to cite

APA:

Hannig, F., & Teich, J. (2005). Output Serialization for FPGA-based and Coarse-grained Processor Arrays. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (pp. 78-84). Las Vegas, NV, US.

MLA:

Hannig, Frank, and Jürgen Teich. "Output Serialization for FPGA-based and Coarse-grained Processor Arrays." Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA ), Las Vegas, NV 2005. 78-84.

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