Conference contribution
(Conference Contribution)


High Performance Network-on-Chip Simulation by Interval-based Timing Predictions


Publication Details
Author(s): Roloff S, Hannig F, Teich J
Editor(s): ACM
Publication year: 2017
Conference Proceedings Title: Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia)
ISBN: 978-1-4503-5117-1

Event details
Event: 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia)
Event location: Seoul, Republic of Korea
Start date of the event: 15/10/2017
End date of the event: 20/10/2017
Language: English

Abstract

Current multi- and many-core computer architectures heavily use NoC communication in order to meet the increased bandwidth demands between the processors and for reasons of scalability. For the proper analysis of concurrency, utilization, and workload distribution of parallel multi-media applications running on such NoC-based architectures, high-speed simulation techniques are required. Apart from accurate timing simulation of compute resources, it is of utmost importance also to accurately model the delays caused by the packet-based network communication in order to reliably verify performance numbers, or to identify any bottlenecks of the underlying architecture, or to study workload distribution techniques or routing algorithms. In this paper, we present a novel simulation approach for NoCs that allows to simulate such communication delays equally accurate but much faster in average than on a flit-by-flit basis. We propose novel algorithmic and analytical techniques that predict the transmission intervals dynamically based on the arrival of communication requests, actual congestion in the NoC, routing information, packet lengths, and other parameters. According to such predictions, the simulation time may in many cases be automatically advanced, thus reducing the number of events to process in the simulator to a large extent. The presented NoC simulation technique has been integrated into a system-level multi-core architecture simulator. Experiments in running parallel real-world and multi-media applications on a simulated scalable NoC architecture show that we are able to achieve speedups of three orders of magnitude compared to cycle-accurate NoC simulators, while preserving a timing accuracy of above 95 %.



How to cite
APA: Roloff, S., Hannig, F., & Teich, J. (2017). High Performance Network-on-Chip Simulation by Interval-based Timing Predictions. In ACM (Eds.), Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia). Seoul, Republic of Korea, KR.

MLA: Roloff, Sascha, Frank Hannig, and Jürgen Teich. "High Performance Network-on-Chip Simulation by Interval-based Timing Predictions." Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia), Seoul, Republic of Korea Ed. ACM, 2017.

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