Journal article
(Original article)


Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders


Publication Details
Author(s): Echavarria Gutiérrez JA, Wildermann S, Potwigin E, Teich J
Publication year: 2017
Journal issue: Approximate Computing
ISSN: 1943-0663
eISSN: 1943-0671
Language: English

Abstract

In this paper, we present a novel methodology to calculate the Arithmetic Error Rate (AER) for deterministic approximate adder architectures where the calculation of each output bit is restricted to a subset of the input bits, denoted as visibilities. Such architectures have been widely proposed in the literature and are, e.g., obtained when splitting the carry chain in a carry-propagate adder into partitions each computed by a separate parallel adder, or when removing carry-lookahead operators in a parallel prefix adder. Our contribution is a unified calculus for determining the arithmetic error rate for (a) such deterministic approximate adder architectures making use of visibilities and (b) the general case of arbitrarily (also non-uniformly) distributed input bits.



How to cite
APA: Echavarria Gutiérrez, J.A., Wildermann, S., Potwigin, E., & Teich, J. (2017). Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders. IEEE Embedded Systems Letters, Approximate Computing.

MLA: Echavarria Gutiérrez, Jorge Alfonso, et al. "Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders." IEEE Embedded Systems Letters Approximate Computing (2017).

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