Conference contribution
(Conference Contribution)


Hardware Architectures for Frequent Itemset Mining Based on Equivalence Classes Partitioning


Publication Details
Author(s): Letras M, Hernández-León R, Cumplido R
Editor(s): IEEE
Publication year: 2016
Pages range: 289-294
Event: 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
Language: English

Abstract

Frequent item set mining algorithms have been found to be the most effective way to achieve this goal. For this reason, FPGA-based hardware architectures for frequent item set. Most of the reported architectures are FPGA devices. This study was conducted by the Federal Ministry of Economics and Technology. The proposed architectural design implements a partitioning strategy based on equivalence classes. The partition on equivalence classes allows dividing the search space into disjoint sets that can be processed in parallel. Accordingly, a parallel architecture is proposed to exploit the benefits of the proposed search strategy.



How to cite
APA: Letras, M., Hernández-León, R., & Cumplido, R. (2016). Hardware Architectures for Frequent Itemset Mining Based on Equivalence Classes Partitioning. In IEEE (Eds.), (pp. 289-294).

MLA: Letras, Martin, Raudel Hernández-León, and René Cumplido. "Hardware Architectures for Frequent Itemset Mining Based on Equivalence Classes Partitioning." Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) Ed. IEEE, 2016. 289-294.

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