Evaluating Signed-digit Arithmetic Circuits using Multi-level storing Memristors
Author(s): Fey D, Reichenbach M, Söll C, Weigel R
Publication year: 2016
Pages range: 1-6
Event: HIPEAC Workshop on Memristor Technology, Design, Automation and Computing
Event location: Prague
Signed-digit (SD) arithmetic, e.g. ternary computer arithmetic circuits process trits instead of bits. It is long known that trits, which are using for each digit not only 0 and 1but in addition either 2 or -1, can carry out an addition in a constant number of steps independent of the used word length of the operands. However, corresponding SD arithmetic circuits have not been used in current processors so far due to the missing of fast, dense and CMOS compatible memory cells that can store reliably multiple levels. Memristors offer these features making necessary a re-evaluation of different SD number representations and their corresponding arithmetic circuits realized in CMOS technology. In addition appropriate analogue-to-digital (A/D) and digital-to-analogue (D/A) interfaces between digital CMOS circuits and multi-level memristors are ne-cessary and have to be considered in this investigation. The paper evaluates different SD number represen-tations using digits with three or five levels for the adder. It is concluded that an SD addition using trits and three elementary processing steps is currently the best solution for memristors. This solution is currently implemented in a first hardware demonstrator using commercially available memristor devices, discretely realised A/D and D/A converters which link the memristor registers to an FPGA implementing the SD arithmetic.
FAU Authors / FAU Editors How to cite
APA: Fey, D., Reichenbach, M., Söll, C., & Weigel, R. (2016). Evaluating Signed-digit Arithmetic Circuits using Multi-level storing Memristors. (pp. 1-6).
MLA: Fey, Dietmar, et al. "Evaluating Signed-digit Arithmetic Circuits using Multi-level storing Memristors." Proceedings of the HIPEAC Workshop on Memristor Technology, Design, Automation and Computing, Prague 2016. 1-6.