Novel Image Processing Architecture for 3D Integrated Circuits
Author(s): Pfundt B, Reichenbach M, Fey D, Söll C
Publication year: 2015
Pages range: 5-15
Event: Parallel -Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS)
Event location: Potsdam
Utilizing highly parallel processors for high speed embedded image processing is a well known approach. However, the question of how to provide a sufficiently fast data rate from image sensor to processing unit is still not solved. As Trough-Silicon-Vias (TSV), a new technology for chip stacking, become available, parallel image transmission from the image sensor to processing unit is enabled. Nevertheless, the usage of a new technology requires architectural changes in the processing units.With this technology at hand, we present a novel image preprocessing architecture suitable for image processing in 3D chips stacks. The architecture was developed in parallel with a customized image sensor to make a real assembly possible. It is fully functionally verified and layouted for a 150 nm process. Our performance estimation shows a processing speed of 770 up to 30.000 fps (frames per second) for 5x5 filters.
FAU Authors / FAU Editors How to cite
APA: Pfundt, B., Reichenbach, M., Fey, D., & Söll, C. (2015). Novel Image Processing Architecture for 3D Integrated Circuits. (pp. 5-15).
MLA: Pfundt, Benjamin, et al. "Novel Image Processing Architecture for 3D Integrated Circuits." Proceedings of the Parallel -Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS), Potsdam 2015. 5-15.