Implementation of a High-Speed Flash ADC for High Performance Pipeline ADCs in an 180nm CMOS Process

Löhr R, Kempf M, Ohnhäuser F, Röber J, Weigel R, Bänisch A (2015)

Publication Type: Conference contribution

Publication year: 2015

Conference Proceedings Title: International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)

Event location: Nusa Dua, Bali

DOI: 10.1109/ISPACS.2015.7432788

Abstract

Pipeline Analog to Digital Converters (ADC) use a sub-ADC in each pipeline stage. They require a much higher sampling rate and less accuracy. For that reason Flash ADCs are predestined for sub-ADCs. In this paper a differential Flash ADC is presented for a targeted pipeline ADC with 16 Bit, 200 MS/s and a 1.5 Bit resolution per stage. The overall accuracy of the Flash ADC is 30mV and a typical propagation delay of around 400 ps is achieved. This corresponds to a sampling rate of 2.5 GS/s. In addition, a new numerical method for an effective simulation of the propagation delay and offset is presented.

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How to cite

APA:

Löhr, R., Kempf, M., Ohnhäuser, F., Röber, J., Weigel, R., & Bänisch, A. (2015). Implementation of a High-Speed Flash ADC for High Performance Pipeline ADCs in an 180nm CMOS Process. In International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS). Nusa Dua, Bali.

MLA:

Löhr, Robert, et al. "Implementation of a High-Speed Flash ADC for High Performance Pipeline ADCs in an 180nm CMOS Process." Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), Nusa Dua, Bali 2015.

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