FPGA-Based Accelerator Design from a Domain-Specific Language
Author(s): Özkan MA, Reiche O, Hannig F, Teich J
Publication year: 2016
Conference Proceedings Title: Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL)
Event: 26th International Conference on Field-Programmable Logic and Applications (FPL)
Event location: Lausanne
Start date of the event: 29/08/2016
End date of the event: 02/09/2016
A large portion of image processing applications often come with stringent requirements regarding performance, energy efficiency, and power. FPGAs have proven to be among the most suitable architectures for algorithms that can be processed in a streaming pipeline. Yet, designing imaging systems for FPGAs remains a very time consuming task. High-Level Synthesis, which has significantly improved due to recent advancements, promises to overcome this obstacle. In particular, Altera OpenCL is a handy solution for employing an FPGA in a heterogeneous system as it covers all device communication. However, to obtain efficient hardware implementations, extreme code modifications, contradicting OpenCL’s data-parallel programming paradigm, are necessary. In this work, we explore the programming methodology that yields significantly better hardware implementations for the Altera Offline Compiler. We furthermore designed a compiler back end for a domain-specific source-to-source compiler to leverage the algorithm description to a higher level and generate highly optimized OpenCL code. Moreover, we advanced the compiler to support arbitrary bit width operations, which are fundamental to hardware designs. We evaluate our approach by discussing the resulting implementations throughout an extensive application set and comparing them with example designs, provided by Altera. In addition, as we can derive multiple implementations for completely different target platforms from the same domain-specific language source code, we present a comparison of the achieved implementations in contrast to GPU implementations.
FAU Authors / FAU Editors Focus Area of Individual Faculties How to cite
APA: Özkan, M.A., Reiche, O., Hannig, F., & Teich, J. (2016). FPGA-Based Accelerator Design from a Domain-Specific Language. In Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL).
MLA: Özkan, Mehmet Akif, et al. "FPGA-Based Accelerator Design from a Domain-Specific Language." Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL), Lausanne 2016.