Automatic and Optimized Generation of Compiled High-Speed RTL Simulators

Hannig F, Kupriyanov O, Teich J (2004)

Publication Type: Conference contribution

Publication year: 2004

Conference Proceedings Title: Proceedings of the Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES 2004)

Event location: Washington, DC

Authors with CRIS profile

Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Dedizierte massiv parallele Systeme (PARO) Jan. 3, 2000 - Jan. 3, 2003

How to cite

APA:

Hannig, F., Kupriyanov, O., & Teich, J. (2004). Automatic and Optimized Generation of Compiled High-Speed RTL Simulators. In Proceedings of the Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES 2004). Washington, DC, US.

MLA:

Hannig, Frank, Olexiy Kupriyanov, and Jürgen Teich. "Automatic and Optimized Generation of Compiled High-Speed RTL Simulators." Proceedings of the Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES 2004), Washington, DC 2004.

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