Conference contribution
(Conference Contribution)


Runtime reconfigurable bus arbitration for concurrent applications on heterogeneous MPSoC architectures


Publication Details
Author(s): Sousa É, Gangadharan D, Hannig F, Teich J
Publisher: Institute of Electrical and Electronics Engineers Inc.
Publication year: 2014
Conference Proceedings Title: Proceedings of the EUROMICRO Digital System Design Conference (DSD)
Pages range: 74-81
ISBN: 9781479957934

Event details
Event: 17th Euromicro Conference on Digital System Design, DSD 2014
Event location: Verona
Start date of the event: 27/08/2014
End date of the event: 29/08/2014

Abstract

This paper describes a runtime reconfigurable bus arbitration technique for concurrent applications on heterogeneous MPSoC architectures. Here, a hardware/software approach is introduced as part of a runtime framework that enables selecting and adapting different policies (i. e., fixed-priority, TDMA, and Round-Robin) such that the performance goals of concurrent applications can be satisfied. To evaluate the hardware cost, we compare our proposed solution with respect to a well-known SPARC V8 architecture supporting fixed-priority arbitration. Notably, even providing the flexibility for selecting up to three different policies, our reconfigurable arbiter needs only 25% and 7% more LUTs and slices registers, respectively. The reconfiguration overhead for changing between different policies is 56 cycles and for programming new time slots, only 28 cycles are necessary. For demonstrating the benefits of this reconfiguration framework, we setup a mixed hard/soft real-time scenario by considering four applications with different timeliness requirements. The experimental results show that by reconfiguring the arbiter, less processing elements can be used for achieving a specific target frame rate. Moreover, adjusting the time slots for TDMA, we can speedup a soft real-time algorithm while still satisfying the deadline for hard real-time applications.



How to cite
APA: Sousa, É., Gangadharan, D., Hannig, F., & Teich, J. (2014). Runtime reconfigurable bus arbitration for concurrent applications on heterogeneous MPSoC architectures. In Proceedings of the EUROMICRO Digital System Design Conference (DSD) (pp. 74-81). Verona, IT: Institute of Electrical and Electronics Engineers Inc..

MLA: Sousa, Éricles, et al. "Runtime reconfigurable bus arbitration for concurrent applications on heterogeneous MPSoC architectures." Proceedings of the 17th Euromicro Conference on Digital System Design, DSD 2014, Verona Institute of Electrical and Electronics Engineers Inc., 2014. 74-81.

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