A highly parameterizable parallel processor array architecture

Kissler D, Kupriyanov O, Hannig F, Teich J (2006)

Publication Status: Published

Publication Type: Conference contribution, Conference Contribution

Publication year: 2006

Pages Range: 105-112

Article Number: 4042422

Conference Proceedings Title: Proceedings of the IEEE International Conference on Field Programmable Technology (FPT 2006)

Event location: Bangkok

ISBN: 9780780397286

DOI: 10.1109/FPT.2006.270293

Abstract

In this paper a new class of highly parameterizable coarse-grained reconfigurable architectures called weakly programmable processor arrays is discussed. The main advantages of the proposed architecture template are the possibility of partial and differential reconfiguration and the systematical classification of different architectural parameters which allow to trade-off flexibility and hardware cost. The applicability of our approach is tested in a case study with different interconnect topologies on an FFGA platform. The results show substantial flexibility gains with only marginal additional hardware cost. © 2006 IEEE.

Authors with CRIS profile

Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Co-Design of Massively Parallel Embedded Processor Architectures (CoMap) Jan. 1, 2005 - Dec. 31, 2011

How to cite

APA:

Kissler, D., Kupriyanov, O., Hannig, F., & Teich, J. (2006). A highly parameterizable parallel processor array architecture. In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT 2006) (pp. 105-112). Bangkok, TH.

MLA:

Kissler, Dmitrij, et al. "A highly parameterizable parallel processor array architecture." Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, FPT 2006, Bangkok 2006. 105-112.

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