Article in Edited Volumes


Robustness Analysis of Watermark Verification Techniques for FPGA Netlist Cores


Publication Details
Author(s): Ziener D, Schmid M, Teich J
Title edited volumes: Design Methodologies for Secure Embedded Systems
Publisher: Springer Verlag
Publishing place: Berlin
Publication year: 2010
Title of series: Lecture Notes in Electrical Engineering
Volume: 78
Pages range: 105-127
ISBN: 978-3-642-16766-9
ISSN: 1876-1100

Abstract

In this paper we analyze the robustness of watermarking techniques for FPGA IP cores against attacks. Unlike most existing watermarking techniques, the focus of our techniques lies on ease of verification, even if the protected cores are embedded into a product. Moreover, we have concentrated on higher abstraction levels for embedding the watermark, particularly at the logic level, where IP cores are distributed as netlist cores. With the presented watermarking methods, it is possible to watermark IP cores at the logic level and identify them with a high likelihood and in a reproducible way in a purchased product from a company that is suspected to have committed IP fraud. For robustness analysis we enhanced a theoretical watermarking model, originally introduced for multimedia watermarking. Finally, two exemplary watermarking techniques for netlist cores using different verification strategies are described and the robustness against attacks is analyzed. © 2010 Springer-Verlag Berlin Heidelberg.



How to cite
APA: Ziener, D., Schmid, M., & Teich, J. (2010). Robustness Analysis of Watermark Verification Techniques for FPGA Netlist Cores. In Design Methodologies for Secure Embedded Systems (pp. 105-127). Berlin: Springer Verlag.

MLA: Ziener, Daniel, Moritz Schmid, and Jürgen Teich. "Robustness Analysis of Watermark Verification Techniques for FPGA Netlist Cores." Design Methodologies for Secure Embedded Systems Berlin: Springer Verlag, 2010. 105-127.

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