Conference contribution


Multiplexing Methods for Power Watermarking


Publication Details
Author(s): Ziener D, Baueregger F, Teich J
Title edited volumes: Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010
Publication year: 2010
Conference Proceedings Title: Proc. IEEE Int. Symposium on Hardware-Oriented Security and Trust
Pages range: 54-59

Event details
Event: IEEE Int. Symposium on Hardware-Oriented Security and Trust (HOST'10)
Event location: Anaheim
Start date of the event: 13/06/2010
End date of the event: 14/06/2010

Abstract

In this paper, we present several enhancements to power watermarking that allow to simultaneously transmit and verify multiple signatures. Power watermarking of netlist IP cores for FPGA architectures is used for detecting IP fraud where the signature (watermark) is transmitted over the power supply pins of the FPGA. Many (watermarked) IP cores can be combined in an FPGA design, which raises the question of how multiple signatures can be detected using the same set of pins. As a solution, we propose multiplexing techniques for power side channel communication, so that all watermarked cores inside the FPGA can be identified to establish a proof of authorship. We analyze different multiplexing methods in order to adapt them to power watermarking and provide experimental results with several cores concurrently transmitting signatures. ©2010 IEEE.



How to cite
APA: Ziener, D., Baueregger, F., & Teich, J. (2010). Multiplexing Methods for Power Watermarking. In Proc. IEEE Int. Symposium on Hardware-Oriented Security and Trust (pp. 54-59). Anaheim, US.

MLA: Ziener, Daniel, Florian Baueregger, and Jürgen Teich. "Multiplexing Methods for Power Watermarking." Proceedings of the IEEE Int. Symposium on Hardware-Oriented Security and Trust (HOST'10), Anaheim 2010. 54-59.

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