Conference contribution


Identifying FPGA IP-Cores based on Lookup Table Content Analysis


Publication Details
Author(s): Ziener D, Aßmus Stefan AS, Teich J
Title edited volumes: Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL
Publication year: 2006
Conference Proceedings Title: Proceedings of 16th International Conference on Field Programmable Logic and Applications
Pages range: 481-486

Event details
Event: 16th International Conference on Field Programmable Logic and Applications
Event location: Madrid
Start date of the event: 28/08/2006
End date of the event: 30/08/2006

Abstract

In this paper we introduce a new method to identify IP cores in an FPGA by analyzing the content of lookup tables. This techniques can be used to identify registered cores for IP protection against unlicensed usage. We show methods to extract the content of the lookup tables in a design from a binary bitfile of Xilinx Virtex-II and Virtex-II Pro FPGAs. To identify a core, we compare the number of unique functions from lookup tables of the core with the lookup tables extracted from a product with an FPGA from an accused company. Also placement information can be used for increasing the reliability of the result. With these methods, no additional sources or information must be inquired from the accused company. These techniques can be used for netlist and bitfile cores, so a wide spectrum of cores can be identified. © 2006 IEEE.



How to cite
APA: Ziener, D., Aßmus Stefan, A.S., & Teich, J. (2006). Identifying FPGA IP-Cores based on Lookup Table Content Analysis. In Proceedings of 16th International Conference on Field Programmable Logic and Applications (pp. 481-486). Madrid, ES.

MLA: Ziener, Daniel, Aßmus Stefan Aßmus Stefan, and Jürgen Teich. "Identifying FPGA IP-Cores based on Lookup Table Content Analysis." Proceedings of the 16th International Conference on Field Programmable Logic and Applications, Madrid 2006. 481-486.

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