3D Exploration of Software Schedules for DSP Algorithms
Bhattacharyya SS, Teich J, Zitzler E (1999)
Publication Type: Conference contribution
Publication year: 1999
Publisher: IEEE
Edited Volumes: Hardware/Software Codesign - Proceedings of the International Workshop
Pages Range: 168-172
Conference Proceedings Title: Proc. CODES'99, the 7th Int. Workshop on Hardware/Software Co-Design
Event location: Rome
Abstract
This paper addresses the problem of exploring tradeoffs between program memory, data memory and execution time requirements (3D) for DSP algorithms specified by data flow graphs. Such an exploration is of utmost importance for being able to analyze the feasibility and range of possible software solutions as part of a hardware/software codesign methodology where the target processor and the code generation style may lead to complete different solutions of the same specification. For solving this multi-objective optimization problem, an Evolutionary Algorithm approach is applied. In particular, a new Pareto-optimization algorithm is introduced. For different well-known target DSP processors, the Pareto-fronts are analyzed and compared.
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APA:
Bhattacharyya, S.S., Teich, J., & Zitzler, E. (1999). 3D Exploration of Software Schedules for DSP Algorithms. In Proc. CODES'99, the 7th Int. Workshop on Hardware/Software Co-Design (pp. 168-172). Rome, IT: IEEE.
MLA:
Bhattacharyya, Shuvra S., Jürgen Teich, and Eckart Zitzler. "3D Exploration of Software Schedules for DSP Algorithms." Proceedings of the 7th Int. Workshop on Hardware/Software Co-Design,, Rome IEEE, 1999. 168-172.
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