Dr.-Ing. Frank Hannig

Thomson Researcher ID: G-5213-2014
Scopus Author ID: 6602533567


Project lead
1 of 3

Integration and Coupling of Tightly Coupled Processor Arrays (T01)
Third Party Funds Group - Sub project
(01/03/2017 - 29/02/2020)

Parallelization and Resource Estimation of Algorithms for Heterogeneous FAS Architectures
Third party funded individual grant
(01/05/2015 - 30/04/2018)

Simulative Design Space Exploration (C02)
Third Party Funds Group - Sub project
(01/07/2014 - 30/06/2018)

ExaStencils - Advanced Stencil-Code Engineering
Third Party Funds Group - Sub project
(01/01/2013 - 31/12/2018)



Project member

ExaStencils - Advanced Stencil-Code Engineering
Third Party Funds Group - Sub project
(01/01/2013 - 31/12/2018)

Compilation and Code Generation for Invasive Programs (C03)
Third Party Funds Group - Sub project
(01/07/2010 - 30/06/2018)


Publications (Download BibTeX)
1 of 9

Conference contribution
Brand M, Hannig F, Tanase AP, et al. (2017)
Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors
IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-17)

Journal article
Khdr H, Pagani S, Sousa É, et al. (2017)
Power Density-Aware Resource Management for Heterogeneous Tiled Multicores
IEEE Transactions on Computers -

Journal article
Unat D, Dubey A, Hoefler T, et al. (2017)
Trends in Data Locality Abstractions for HPC Systems
IEEE Transactions on Parallel and Distributed Systems

Conference contribution
Brand M, Hannig F, Tanase AP, et al. (2017)
Efficiency in ILP Processing by Using Orthogonality
The 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2017)

Conference contribution
Reiche O, Özkan MA, Membarth R, et al. - Ed.: IEEE (2017)
Generating FPGA-based Image Processing Accelerators with Hipacc
Proceedings of the International Conference On Computer Aided Design

Conference contribution
Fickenscher J, Reinhart S, Bouzouraa ME, et al. - Ed.: IEEE (2017)
Convoy Tracking for ADAS on Embedded GPUs
Intelligent Vehicles Symposium (IV 2017)

Unpublished / Preprint
Schmitt C, Schmid M, Kuckuk S, et al. (2017)
Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution
Parallel Processing Letters

Journal article
Tanase AP, Witterauf M, Teich J, et al. (2017)
Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays
ACM Transactions on Embedded Computing Systems

Conference contribution
Özkan MA, Reiche O, Hannig F, et al. (2017)
Hardware Design and Analysis of Efficient Loop Coarsening and Border Handling for Image Processing
28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)

Journal article
Köstler H, Schmitt C, Kuckuk S, et al. (2017)
A Scala Prototype to Generate Multigrid Solver Implementations for Different Problems and Target Multi-Core Platforms
International Journal of Computational Science and Engineering

Conference contribution
Witterauf M, Hannig F, Teich J (2017)
Constructing Fast and Cycle-Accurate Simulators for Configurable Accelerators Using C++ Templates
Proceedings of the Symposium on Rapid System Prototyping

Conference contribution
Özkan MA, Reiche O, Hannig F, et al. (2017)
A Highly Efficient and Comprehensive Image Processing Library for C++-based High-Level Synthesis
Proceedings of the Fourth International Workshop on FPGAs for Software Programmers (FSP)

Conference contribution
Roloff S, Hannig F, Teich J - Ed.: ACM (2017)
High Performance Network-on-Chip Simulation by Interval-based Timing Predictions
Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia)

Conference contribution
Reiche O, Kobylko C, Hannig F, et al. - Ed.: ACM (2017)
Auto-vectorization for Image Processing DSLs
Proceedings of the 18th International Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES)

Journal article
Reiche O, Özkan MA, Hannig F, et al. (2017)
Loop Parallelization Techniques for FPGA Accelerator Synthesis
Journal of Signal Processing Systems

Conference contribution
Roloff S, Pöppl A, Schwarzer T, et al. (2016)
ActorX10: An Actor Library for X10
Proceedings of the 6th ACM SIGPLAN X10 Workshop (X10)

Article in Edited Volumes
Schmid M, Schmitt C, Hannig F, et al. - Ed.: Dirk Koch, Frank Hannig, and Daniel Ziener (2016)
Big Data and HPC Acceleration with Vivado HLS
FPGAs for Software Programmers

Journal article
Bhadouria VS, Tanase AP, Schmid M, et al. (2016)
A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators
Journal of Signal Processing Systems

Article in Edited Volumes
Schmid M, Reiche O, Hannig F, et al. - Ed.: Dirk Koch, Frank Hannig, and Daniel Ziener (2016)
HIPAcc
FPGAs for Software Programmers

Conference contribution
Häublein K, Reichenbach M, Reiche O, et al. (2016)
Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures
Proceedings of the 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)

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Last updated on 2016-05-27 at 05:02
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