Ultra-Low Power 60 GHz Class-C Frequency Tripler in 22-nm FDSOI CMOS Technology
Gupta A, Dietz M, Engelmann A, Hagelauer A (2024)
Publication Language: English
Publication Status: Accepted
Publication Type: Unpublished / Preprint
Future Publication Type: Conference contribution
Publication year: 2024
Event location: Punta Del Este
Abstract
This paper presents a 60 GHz class-C frequency tripler, implemented in 22-nm FDSOI (fully depleted silicon- on-insulator) CMOS technology, for ultra-low power and highly integrated radios used in millimeter-wave indoor localization ap- plications. The tripler employs a multi-stage transformer-coupled differential design with band-pass filters to selectively extract and amplify the power at the 3rd harmonic (3f0) tone while attenuating powers at fundamental (f0) and second harmonic (2f0) tones. An integrated bias generator with resistor trimming, improves the tripler robustness to the on-chip process and mismatch variations. The tripler exhibits a maximum conversion gain (CG) and peak conversion efficiency (CE) of -0.7 dB and 12.63%, respectively, at 60 GHz, and a 3-dB bandwidth of 3.6 GHz with a total DC power consumption (PDC) of 7.9 mW at 0.8 V supply. A harmonic rejection ratio (HRR) exceeding 45 dB for fundamental and second harmonic tones is achieved. The maximum saturated output power (PSAT) obtained is 0.9 dBm. The circuit occupies 0.4 mm² area, including pads.
Authors with CRIS profile
Aditya Gupta
Lehrstuhl für Technische Elektronik
Andre Engelmann
Lehrstuhl für Technische Elektronik
Involved external institutions
Germany (DE)How to cite
APA:
Gupta, A., Dietz, M., Engelmann, A., & Hagelauer, A. (2024). Ultra-Low Power 60 GHz Class-C Frequency Tripler in 22-nm FDSOI CMOS Technology. (Unpublished, Accepted).
MLA:
Gupta, Aditya, et al. Ultra-Low Power 60 GHz Class-C Frequency Tripler in 22-nm FDSOI CMOS Technology. Unpublished, Accepted. 2024.
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