Employing polyhedral methods to optimize stencils on FPGAs with stencil-specific caches, data reuse, and wide data bursts [Reproduction Package]

Mayer F, Brandner J, Philippsen M (2024)


Publication Language: English

Publication Type: Other publication type, Forschungsdaten

Publication year: 2024

DOI: 10.5281/zenodo.10396084

Open Access Link: https://doi.org/10.5281/zenodo.10396084

Abstract

This archive contains the the benchmark data and source code described in the conference paper "Employing polyhedral methods to optimize stencils on FPGAs with stencil-specific caches, data reuse, and wide data bursts" (In Proc. 14th Intl. Workshop on Polyhedral Compilation Techniques), Munich, Germany, Jan. 2024.

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How to cite

APA:

Mayer, F., Brandner, J., & Philippsen, M. (2024). Employing polyhedral methods to optimize stencils on FPGAs with stencil-specific caches, data reuse, and wide data bursts [Reproduction Package].

MLA:

Mayer, Florian, Julian Brandner, and Michael Philippsen. Employing polyhedral methods to optimize stencils on FPGAs with stencil-specific caches, data reuse, and wide data bursts [Reproduction Package]. 2024.

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