More Efficient CMMs on FPGAs: Instantiated Ternary Adders for Computation Coding

Lehnert A, Rosenberger H, Müller R, Reichenbach M (2023)


Publication Type: Book chapter / Article in edited volumes

Publication year: 2023

Journal

Edited Volumes: Applied Reconfigurable Computing. Architectures, Tools, and Applications

Pages Range: 275-289

ISBN: 9783031429200

DOI: 10.1007/978-3-031-42921-7_19

Abstract

With the ever increasing complexity of modern algorithms, especially Artificial Neural Networks, the acceleration of linear operations becomes highly beneficial. Computation Coding (CC) matrix decomposition methods promise great reductions in operational cost of Constant Matrix Multiplication. Implementations of such decompositions rely on shifts followed by additions only. Recent FPGAs enable efficient addition of three operands by using multiple-output Lookup-Tables (LUTs) and CC decompositions naturally enable fine control over operand counts in each addition. However, synthesis does not always infer these efficient adder structures.

To better utilize the resources present on FPGAs, we use primitive instantiation via a Python-based hardware generation framework allowing for fine control over implemented logic. We show, that designs based on instantiated primitive ternary-input adders reduce hardware cost in LUTs by up to 1.8×

 compared to inferred designs and decompositions based on binary input adders only, but also perform well with regards to pipelining and timing restrictions.

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How to cite

APA:

Lehnert, A., Rosenberger, H., Müller, R., & Reichenbach, M. (2023). More Efficient CMMs on FPGAs: Instantiated Ternary Adders for Computation Coding. In Applied Reconfigurable Computing. Architectures, Tools, and Applications. (pp. 275-289).

MLA:

Lehnert, Alexander, et al. "More Efficient CMMs on FPGAs: Instantiated Ternary Adders for Computation Coding." Applied Reconfigurable Computing. Architectures, Tools, and Applications. 2023. 275-289.

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