Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks using Multi-Reader Buffers

Letras M, Falk J, Teich J (2023)

Publication Type: Conference contribution, Original article

Publication year: 2023

City/Town: Germany

Conference Proceedings Title: Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023)

Event location: Toulouse

URI: https://drops.dagstuhl.de/opus/volltexte/2023/17737/

DOI: 10.4230/OASIcs.NG-RES.2023.6

Authors with CRIS profile

Mauro Martin Letras Luna Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

SystemCoDesigner: System level design space exploration for embedded systems (SystemCoDesigner) April 1, 2005 - April 1, 2008

How to cite

APA:

Letras, M., Falk, J., & Teich, J. (2023). Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks using Multi-Reader Buffers. In Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023). Toulouse, FR: Germany.

MLA:

Letras, Martin, Joachim Falk, and Jürgen Teich. "Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks using Multi-Reader Buffers." Proceedings of the Fourth Workshop on Next Generation Real-Time Embedded Systems, Toulouse Germany, 2023.

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