Design optimisation of a 1 MHz half-bridge CLL resonant converter

Mao M, Tchobanov D, Li D, März M (2008)

Publication Type: Journal article

Publication year: 2008

Journal

Iet Power Electronics The Institution of Engineering and Technology

Book Volume: 1

Pages Range: 100-108

Journal Issue: 1

DOI: 10.1049/iet-pel:20070061

Abstract

A detailed design optimisation for the CLL resonant converter is presented and zero-voltage switching (ZVS) of MOSFETs is guaranteed in overall operation ranges. A series of analysis and calculations are presented to choose an ideal value of the loaded quality factor meeting the requirement of ZVS behaviour (inductive load and full discharge of the output capacitance of a MOSFET), ensuring the desired maximum voltage gain and optimal design with high efficiency at normal operation point. Corresponding illustrations are provided to clearly show the analysis result. The developed design optimisation method has been implemented into a 1 MHz CLL resonant converter prototype. It is designed to operate with an output voltage of 24 V and full load output power of 250 W. The maximum efficiency reaches 93% and power density reaches 32 W/inch3. Therefore the proposed converter is suitable for high efficiency and high power density applications such as LCD and PDP TV power module.

Authors with CRIS profile

Martin März

Involved external institutions

Nanjing University of Aeronautics and Astronautics (NUAA) / 南京航空航天大学 CN China (CN) Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie (IISB) DE Germany (DE) Tongji University / 同济大学 CN China (CN)

How to cite

APA:

Mao, M., Tchobanov, D., Li, D., & März, M. (2008). Design optimisation of a 1 MHz half-bridge CLL resonant converter. Iet Power Electronics, 1(1), 100-108. https://dx.doi.org/10.1049/iet-pel:20070061

MLA:

Mao, M., et al. "Design optimisation of a 1 MHz half-bridge CLL resonant converter." Iet Power Electronics 1.1 (2008): 100-108.

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