A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic

Lakshmi V, Reuben JR, Pudi V (2021)

Publication Type: Journal article

Publication year: 2021

Journal

IEEE Transactions on Circuits and Systems I-Regular Papers Institute of Electrical and Electronics Engineers (IEEE)

DOI: 10.1109/TCSI.2021.3129827

Abstract

In-memory computing using emerging technologies such as resistive random-access memory (ReRAM) addresses the `von Neumann bottleneck' and strengthens the present research impetus to overcome the memory wall. While many methods have been recently proposed to implement Boolean logic in memory, the latency of arithmetic circuits (adders and consequently multipliers) implemented as a sequence of such Boolean operations increases greatly with bit-width. Existing in-memory multipliers require O(n²) cycles which is inefficient both in terms of latency and energy. In this work, we tackle this exorbitant latency by adopting Wallace Tree multiplier architecture and optimizing the addition operation in each phase of the Wallace Tree. Majority logic primitive was used for addition since it is better than NAND/NOR/IMPLY primitives. Furthermore, high degree of gate-level parallelism is employed at the array level by executing multiple majority gates in the columns of the array. In this manner, an in-memory multiplier of O(n.log(n)) latency is achieved which outperforms all reported in-memory multipliers. Furthermore, the proposed multiplier can be implemented in a regular transistor-accessed memory array without any major modifications to its peripheral circuitry and is also energy-efficient.

Authors with CRIS profile

John Reuben Prabahar Lehrstuhl für Informatik 3 (Rechnerarchitektur)

Involved external institutions

Indian Institute of Technology Tirupati (IITTP) / ఇండియన్ ఇన్స్టిట్యూట్ ఆఫ్ టెక్నోలజీ తిరుపతి IN India (IN)

How to cite

APA:

Lakshmi, V., Reuben, J.R., & Pudi, V. (2021). A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic. IEEE Transactions on Circuits and Systems I-Regular Papers. https://dx.doi.org/10.1109/TCSI.2021.3129827

MLA:

Lakshmi, Vijaya, John Reuben Reuben, and Vikramkumar Pudi. "A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic." IEEE Transactions on Circuits and Systems I-Regular Papers (2021).

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