Reducing Reconfiguration Time in FPGAs

Sadeghi M, Razavi SA, Saheb Zamani M (2019)

Publication Language: English

Publication Type: Conference contribution, Original article

Publication year: 2019

Publisher: IEEE

City/Town: 2019 27th Iranian Conference on Electrical Engineering (ICEE)

Pages Range: 4

Conference Proceedings Title: Iranian Conference on Electrical Engineering (ICEE)

Event location: Yazd, Iran IR

ISBN: 978-1-7281-1508-5

URI: https://ieeexplore.ieee.org/abstract/document/8786689

DOI: 10.1109/IranianCEE.2019.8786689

Abstract

Despite the growing popularity of field-programmable gate arrays (FPGA), this technology still suffers from drawbacks such as larger area, higher power consumption and longer runtime than application-specific integrated circuits (ASIC). Reconfiguration capability gives FPGAs an advantage over ASIC and can make it a more appropriate option for implementing some applications. One important issue regarding the reconfiguration process is the time it takes to carry out this procedure. This paper seeks to accelerate the reconfiguration process by using a bitstream compression method with a primary focus on FPGA architecture. Since multiplexers are among the main components of FPGAs, the proposed method is focused on encoding and compression of configuration bitstream for such resources. In addition, the bitstream format and the decompression operation are designed to obtain desirable results in terms of area overhead and time improvement. Results of experiments show that in comparison to the basic scheme, the proposed design improves the reconfiguration time by 33%.

Authors with CRIS profile

Misha Sadeghi Sonderforschungsbereich 1483/1 Empathokinästhetische Sensorik – Sensortechniken und Datenanalyseverfahren zur empathokinästhetischen Modellbildung und Zustandsbestimmung

Involved external institutions

University of California Irvine US United States (USA) (US) Amirkabir University of Technology (AUT) / دانشگاه صنعتی امیرکبیر IR Iran, Islamic Republic of (IR)

How to cite

APA:

Sadeghi, M., Razavi, S.A., & Saheb Zamani, M. (2019). Reducing Reconfiguration Time in FPGAs. In Iranian Conference on Electrical Engineering (ICEE) (pp. 4). Yazd, Iran, IR: 2019 27th Iranian Conference on Electrical Engineering (ICEE): IEEE.

MLA:

Sadeghi, Misha, Seyyed Ahmad Razavi, and Morteza Saheb Zamani. "Reducing Reconfiguration Time in FPGAs." Proceedings of the 27th Iranian Conference on Electrical Engineering (ICEE), Yazd, Iran 2019 27th Iranian Conference on Electrical Engineering (ICEE): IEEE, 2019. 4.

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