Prabahar JR, Fey D (2021)
Publication Type: Conference contribution
Publication year: 2021
Publisher: IEEE Computer Society
Book Volume: 2021-July
Pages Range: 157-163
Conference Proceedings Title: Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Event location: Tampa, FL, USA
ISBN: 9781665439466
DOI: 10.1109/ISVLSI51109.2021.00038
The movement of data between processing and memory units, often referred to as the 'von Neumann bottleneck' is the main reason for the degraded performance of contemporary computing systems. In an effort to overcome this bottleneck, methods to 'compute' at the location of data are being pursued in many emerging memories, including Resistive RAM (ReRAM). Although many prior works have pursued addition in memory, the latency of n-bit addition has not been judiciously optimized, resulting in O(n) or at best O(log(n)). Computing with three states can enable carry-free addition and result in a latency which is independent of operand width (O(1)). In this work, we propose a method to perform carry-free addition completely in memory (a storage array, a processing array and their peripheral circuitry). The proposed technique incurs a latency of 22 memory cycles, which outperforms other in-memory binary adders for n = 32. This speed is achieved at the cost of increased peripheral hardware.
APA:
Prabahar, J.R., & Fey, D. (2021). Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles. In Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI (pp. 157-163). Tampa, FL, USA: IEEE Computer Society.
MLA:
Prabahar, John Reuben, and Dietmar Fey. "Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles." Proceedings of the 20th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021, Tampa, FL, USA IEEE Computer Society, 2021. 157-163.
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