Simulating large neural networks embedding MLC RRAM as weight storage considering device variations

Fritscher M, Knödtel J, Reiser D, Mallah M, Pechmann S, Fey D, Reichenbach M (2021)

Publication Type: Conference contribution, Original article

Publication year: 2021

Conference Proceedings Title: Proc. of 12th IEEE Latin America Symposium on Circuits and System

DOI: 10.1109/lascas51355.2021.9459159

Authors with CRIS profile

Johannes Knödtel Lehrstuhl für Informatik 3 (Rechnerarchitektur) Daniel Reiser Lehrstuhl für Informatik 3 (Rechnerarchitektur) Stefan Pechmann Lehrstuhl für Technische Elektronik Dietmar Fey Lehrstuhl für Informatik 3 (Rechnerarchitektur) Marc Reichenbach Lehrstuhl für Informatik 3 (Rechnerarchitektur)

Involved external institutions

Fraunhofer-Institut für Integrierte Schaltungen (IIS) DE Germany (DE)

How to cite

APA:

Fritscher, M., Knödtel, J., Reiser, D., Mallah, M., Pechmann, S., Fey, D., & Reichenbach, M. (2021). Simulating large neural networks embedding MLC RRAM as weight storage considering device variations. In Proc. of 12th IEEE Latin America Symposium on Circuits and System.

MLA:

Fritscher, Markus, et al. "Simulating large neural networks embedding MLC RRAM as weight storage considering device variations." Proceedings of the Proc. of 12th IEEE Latin America Symposium on Circuits and System 2021.

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