Vertical architecture for enhancement mode power transistors based on GaN nanowires

Yu F, Ruemmler D, Hartmann J, Caccamo L, Schimpke T, Strassburg M, Gad AE, Bakin A, Wehmann HH, Witzigmann B, Wasisto HS, Waag A (2016)

Publication Type: Journal article

Publication year: 2016

Journal

Applied Physics Letters American Institute of Physics (AIP)

Book Volume: 108

Article Number: 213503

Journal Issue: 21

DOI: 10.1063/1.4952715

Abstract

The demonstration of vertical GaN wrap-around gated field-effect transistors using GaN nanowires is reported. The nanowires with smooth a-plane sidewalls have hexagonal geometry made by top-down etching. A 7-nanowire transistor exhibits enhancement mode operation with threshold voltage of 1.2 V, on/off current ratio as high as 108, and subthreshold slope as small as 68 mV/dec. Although there is space charge limited current behavior at small source-drain voltages (Vds), the drain current (Id) and transconductance (gm) reach up to 314 mA/mm and 125 mS/mm, respectively, when normalized with hexagonal nanowire circumference. The measured breakdown voltage is around 140 V. This vertical approach provides a way to next-generation GaN-based power devices.

Authors with CRIS profile

Bernd Witzigmann

Involved external institutions

Technische Universität Braunschweig DE Germany (DE) Osram Opto Semiconductors GmbH DE Germany (DE) Universität Kassel DE Germany (DE)

How to cite

APA:

Yu, F., Ruemmler, D., Hartmann, J., Caccamo, L., Schimpke, T., Strassburg, M.,... Waag, A. (2016). Vertical architecture for enhancement mode power transistors based on GaN nanowires. Applied Physics Letters, 108(21). https://dx.doi.org/10.1063/1.4952715

MLA:

Yu, Feng, et al. "Vertical architecture for enhancement mode power transistors based on GaN nanowires." Applied Physics Letters 108.21 (2016).

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