Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

Fatahilah MF, Yu F, Strempel K, Romer F, Maradan D, Meneghini M, Bakin A, Hohls F, Schumacher HW, Witzigmann B, Waag A, Wasisto HS (2019)

Publication Type: Journal article

Publication year: 2019

Journal

Scientific Reports Nature Publishing Group: Open Access Journals - Option B

Book Volume: 9

Article Number: 10301

Journal Issue: 1

DOI: 10.1038/s41598-019-46186-9

Abstract

This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1–100) and diameters (i.e., 220–640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p-channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage (Vth) of (6.6 ± 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al2O3) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep Vth shift (ΔVth) of ~0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics.

Authors with CRIS profile

Bernd Witzigmann

Involved external institutions

Technische Universität Braunschweig DE Germany (DE) Universität Kassel DE Germany (DE) Physikalisch-Technische Bundesanstalt (PTB) DE Germany (DE) University of Padua / Universita degli Studi di Padova IT Italy (IT)

How to cite

APA:

Fatahilah, M.F., Yu, F., Strempel, K., Romer, F., Maradan, D., Meneghini, M.,... Wasisto, H.S. (2019). Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics. Scientific Reports, 9(1). https://doi.org/10.1038/s41598-019-46186-9

MLA:

Fatahilah, Muhammad Fahlesa, et al. "Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics." Scientific Reports 9.1 (2019).

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