A 12Bit 8GS/s Randomly-Time-Interleaved SAR ADC with Adaptive Mismatch Correction

Linnhoff S, Sippel E, Buballa F, Reinhold M, Vossiek M, Gerfers F (2021)

Publication Language: English

Publication Type: Conference contribution, Conference Contribution

Publication year: 2021

Publisher: IEEE Xplore

Event location: Daegu, Korea (South) KR

ISBN: 978-1-7281-9201-7

DOI: 10.1109/ISCAS51556.2021.9401579

Abstract

This paper presents a wideband 12Bit 8GS/s time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC), featuring a sub-2 radix architecture with an overrange of 10% and randomized sampling with mismatch correction in a 28nm CMOS technology. For this purpose, 18 500MHz SAR-ADCs plus an additional reference ADC are interleaved. This topology enables a randomization approach, reducing mismatch related interleaving spurs. Furthermore, the additional reference ADC operating in parallel to the main ADC enables adaptive digital calibration to correct for static and time-interleaved mismatch effects. A wideband front-end features two subsequent push-pull buffer stages to achieve a high track-and-hold (T/H) bandwidth and high sampling linearity, while improving kickback related settling limitations. After calibration, the ADC achieves a signal to noise and distortion ratio (SNDR) of 56.8dB and a spurious free dynamic range (SFDR) of 80dBc applying a single full scale sine wave tone close to the Nyquist frequency of 4GHz.

Authors with CRIS profile

Erik Sippel Lehrstuhl für Hochfrequenztechnik Martin Vossiek Lehrstuhl für Hochfrequenztechnik

Involved external institutions

Technische Universität Berlin DE Germany (DE) eesy-ic GmbH DE Germany (DE)

How to cite

APA:

Linnhoff, S., Sippel, E., Buballa, F., Reinhold, M., Vossiek, M., & Gerfers, F. (2021). A 12Bit 8GS/s Randomly-Time-Interleaved SAR ADC with Adaptive Mismatch Correction. In 2021 IEEE International Symposium on Circuits and Systems (ISCAS) (Eds.), Proceedings of the International Symposium on Circuits and Systems (ISCAS). Daegu, Korea (South), KR: IEEE Xplore.

MLA:

Linnhoff, Sebastian, et al. "A 12Bit 8GS/s Randomly-Time-Interleaved SAR ADC with Adaptive Mismatch Correction." Proceedings of the International Symposium on Circuits and Systems (ISCAS), Daegu, Korea (South) Ed. 2021 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE Xplore, 2021.

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