A parallel-friendly majority gate to accelerate in-memory computation

Reuben JR, Pechmann S (2020)

Publication Type: Conference contribution

Publication year: 2020

Journal

International Conference on Application-Specific Systems, Architectures and Processors, Proceedings Institute of Electrical and Electronics Engineers

Publisher: Institute of Electrical and Electronics Engineers Inc.

Book Volume: 2020-July

Pages Range: 93-100

Conference Proceedings Title: Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Event location: Manchester GB

ISBN: 9781728171470

DOI: 10.1109/ASAP49362.2020.00025

Abstract

Efforts to combat the 'von Neumann bottleneck' have been strengthened by Resistive RAMs (RRAMs), which enable computation in the memory array. Majority logic can accelerate computation when compared to NAND/NOR/IMPLY logic due to it's expressive power. In this work, we propose a method to compute majority while reading from a transistor-accessed RRAM array. The proposed gate was verified by simulations using a physics-based model (for RRAM) and industry standard model (for CMOS sense amplifier) and, found to tolerate reasonable variations in the RRAMs' resistive states. Together with NOT gate, which is also implemented in-memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. The parallel-friendly nature of the proposed gate is exploited to implement an eight-bit parallel-prefix adder in memory array. The proposed in-memory adder could achieve a latency reduction of 70% and 50% when compared to IMPLY and NAND/NOR logic-based adders, respectively.

Authors with CRIS profile

John Reuben Prabahar Lehrstuhl für Informatik 3 (Rechnerarchitektur)

Involved external institutions

Universität Bayreuth DE Germany (DE)

How to cite

APA:

Reuben, J.R., & Pechmann, S. (2020). A parallel-friendly majority gate to accelerate in-memory computation. In Frank Hannig, Javier Navaridas, Dirk Koch, Ameer Abdelhadi (Eds.), Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors (pp. 93-100). Manchester, GB: Institute of Electrical and Electronics Engineers Inc..

MLA:

Reuben, John Reuben, and Stefan Pechmann. "A parallel-friendly majority gate to accelerate in-memory computation." Proceedings of the 31st IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2020, Manchester Ed. Frank Hannig, Javier Navaridas, Dirk Koch, Ameer Abdelhadi, Institute of Electrical and Electronics Engineers Inc., 2020. 93-100.

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