A Hardware Inference Accelerator for Temporal Convolutional Networks

Ali R, Mallah M, Leyh M, Holzinger P, Breiling M, Reichenbach M, Fey D (2019)

Publication Language: English

Publication Type: Conference contribution, Conference Contribution

Publication year: 2019

Pages Range: 1-7

Conference Proceedings Title: Proceedings of Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2019 IEEE

Event location: Helsinki FI

ISBN: 978-1-7281-2769-9

URI: https://ieeexplore.ieee.org/document/8906963

DOI: 10.1109/NORCHIP.2019.8906963

Abstract

Traditionally, Recurrent Neural Networks (RNNs)are used for time series prediction. However, recent results have shown that Temporal Convolutional Networks (TCNs) outperform RNNs in terms of accuracy and training time. By using dilated convolutions TCNs are able to capture long term temporal dependencies from time series. The use of existing CNN inference accelerators for the computation of dilated convolutions significantly decreases the throughput and causes computation overhead. In order to take into account the one-dimensionality of the convolutions and presence of dilation, this paper proposes a dedicated hardware inference accelerator for TCNs. We use this accelerator to run an adaptation of WaveNet for anomaly detection in an ECG time series data set. Our results show that it can achieve 6.3·10-4 DRAM access/MAC, 0.043 on-chip SRAM access/MAC and the throughput of 8 millisecond/inference. This lower number of on-chip and off-chip memory accesses significantly decreases the overall power consumption and increases the throughput.

Authors with CRIS profile

Philipp Holzinger Lehrstuhl für Informatik 3 (Rechnerarchitektur) Marc Reichenbach Lehrstuhl für Informatik 3 (Rechnerarchitektur) Dietmar Fey Lehrstuhl für Informatik 3 (Rechnerarchitektur)

Involved external institutions

Fraunhofer-Institut für Integrierte Schaltungen (IIS) DE Germany (DE)

How to cite

APA:

Ali, R., Mallah, M., Leyh, M., Holzinger, P., Breiling, M., Reichenbach, M., & Fey, D. (2019). A Hardware Inference Accelerator for Temporal Convolutional Networks. In IEEE (Eds.), Proceedings of Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2019 IEEE (pp. 1-7). Helsinki, FI.

MLA:

Ali, Rashid, et al. "A Hardware Inference Accelerator for Temporal Convolutional Networks." Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), Helsinki Ed. IEEE, 2019. 1-7.

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