ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing

Unveröffentlicht / Preprint


Details zur Publikation

Autor(en): Becher A, Herrmann A, Wildermann S, Teich J
Herausgeber: GI-Edition Lecture Notes in Informatics
Verlag: GI-Edition Lecture Notes in Informatics
Jahr der Veröffentlichung: 2019
Tagungsband: Proceedings of the 1st Workshop on Novel Data Management Ideas on Heterogeneous (Co-)Processors (NoDMC)
Sprache: Englisch


Abstract

Reconfigurable hardware such as Field-programmable Gate Arrays (FPGAs) is widely used for data processing in databases. Most of the related work focuses on
accelerating one or a small set of specific operations like sort, join,
regular expression matching. A drawback of such approaches is often the
assumed static accelerator hardware architecture: Rather than adapting
the hardware to fit the query, the query plan has to be adapted to fit
the hardware. Moreover, operators or data types that are not supported by the accelerator have to be processed in software. As a remedy, approaches for exploiting the
dynamic partial reconfigurability of FPGAs have been proposed that are
able to adapt the datapath at runtime. However, on modern FPGAs, this introduces new challenges due to the heterogeneity of the available resources. In addition, not only the execution resources may be heterogeneous but also the memory resources.


This work focuses on the architectural aspects
of database (co-)processing on heterogeneous FPGA-based PSoC
(programmable System-on-Chip) architectures including processors,
specialized hardware components, multiple memory types and dynamically
partially reconfigurable areas. We present an approach to support such (co-)processing called ReProVide. In particular, we introduce a model to
formalize the challenging task of operator placement and buffer
allocation onto such heterogeneous hardware and describe the
difficulties of finding good placements. Furthermore, a detailed insight into different
memory types and their peculiarities is given in order to use the
strength of heterogeneous memory architectures. Here, we also highlight the implications of heterogeneous memories for the problem of query placement.


FAU-Autoren / FAU-Herausgeber

Becher, Andreas
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Herrmann, Achim
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Wildermann, Stefan Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Zuletzt aktualisiert 2019-08-01 um 13:23