AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs

Beitrag bei einer Tagung
(Originalarbeit)


Details zur Publikation

Autor(en): Echavarria Gutiérrez JA, Wildermann S, Teich J
Jahr der Veröffentlichung: 2018
Tagungsband: Proceedings of 2018 International Conference on Field Programmable Technology
Sprache: Englisch


Abstract

New relaxed quality standards laid down by approximate computing enrich the design pool with architectures dissipating less power, consuming fewer resources or with smaller latencies. In LUTbased FPGA logic approximation, the number of LUTs and latency associated to a design can be optimized by allowing the approximation of circuit results. In this paper, we present techniques for automatic design space exploration (DSE) of Boolean function falsifications and the ability and impact to reduce resources usage as well as the length of critical paths on LUT-based FPGAs. Our experiments give evidence that resource reductions of about 20% are easily achievable for error rates amounting to less than 0.05% w.r.t. accurate designs.


FAU-Autoren / FAU-Herausgeber

Echavarria Gutiérrez, Jorge Alfonso
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Wildermann, Stefan Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Echavarria Gutiérrez, J.A., Wildermann, S., & Teich, J. (2018). AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs. In Proceedings of 2018 International Conference on Field Programmable Technology. Naha, Okinawa, JP.

MLA:
Echavarria Gutiérrez, Jorge Alfonso, Stefan Wildermann, and Jürgen Teich. "AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs." Proceedings of the International Conference on Field Programmable Technology (FPT 2018), Naha, Okinawa 2018.

BibTeX: 

Zuletzt aktualisiert 2018-16-09 um 19:23