AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs
Echavarria Gutiérrez JA, Wildermann S, Teich J (2018)
Publication Language: English
Publication Type: Conference contribution, Original article
Publication year: 2018
Conference Proceedings Title: Proceedings of 2018 International Conference on Field Programmable Technology
Event location: Naha, Okinawa
Abstract
New relaxed quality standards laid down by approximate computing enrich the design pool with architectures dissipating less power, consuming fewer resources or with smaller latencies. In LUTbased FPGA logic approximation, the number of LUTs and latency associated to a design can be optimized by allowing the approximation of circuit results. In this paper, we present techniques for automatic design space exploration (DSE) of Boolean function falsifications and the ability and impact to reduce resources usage as well as the length of critical paths on LUT-based FPGAs. Our experiments give evidence that resource reductions of about 20% are easily achievable for error rates amounting to less than 0.05% w.r.t. accurate designs.
Authors with CRIS profile
Jorge Alfonso Echavarria Gutiérrez
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Stefan Wildermann
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Jürgen Teich
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Related research project(s)
How to cite
APA:
Echavarria Gutiérrez, J.A., Wildermann, S., & Teich, J. (2018). AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs. In Proceedings of 2018 International Conference on Field Programmable Technology. Naha, Okinawa, JP.
MLA:
Echavarria Gutiérrez, Jorge Alfonso, Stefan Wildermann, and Jürgen Teich. "AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs." Proceedings of the International Conference on Field Programmable Technology (FPT 2018), Naha, Okinawa 2018.
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