Run-time Requirement Enforcement for Loop Programs on Processor Arrays

Beitrag bei einer Tagung
(Konferenzbeitrag)


Details zur Publikation

Autor(en): Witterauf M, Teich J
Herausgeber: ACM, IEEE
Jahr der Veröffentlichung: 2018
Tagungsband: Proceedings of the 16th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Seitenbereich: 1-11
Sprache: Englisch


Abstract

Loop bounds are often unknown until run time, making it difficult to analyze non-functional properties such as latency at compile-time.
Similarly, static allocations of processing resources to loop computations might be too conservative with respect to given performance requirements, or not optimal with respect to the energy consumption.

To still satisfy requirements when accelerating loop nests under this uncertainty of loop bounds, we formalize and propose an approach to run-time requirement enforcement:
at run time, select a mapping among a set of candidates that satisfies a given set of requirements while optimizing secondary objectives.
Because the candidate search space of suitable mappings might be prohibitively large to evaluate at run time, we further introduce two approaches to reduce its cardinality:
1) architecture-specific reduction by solving for parts of the mapping from the requirements, and
2) design-time reduction by finding a k-subset of mappings that maximizes the number of loop bounds where the requirements are satisfied.

We implemented our proposed run-time requirement enforcement techniques for a representative class of programmable processor array architecture called Tightly Coupled Procesor Array and demonstrate their effectiveness with a case study.
The case study shows the effectiveness of our approach: We can satisfy given latency requirements while easily saving up to 10% in energy.


FAU-Autoren / FAU-Herausgeber

Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Witterauf, Michael
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Witterauf, M., & Teich, J. (2018). Run-time Requirement Enforcement for Loop Programs on Processor Arrays. In ACM, IEEE (Eds.), Proceedings of the 16th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) (pp. 1-11). Peking, CN.

MLA:
Witterauf, Michael, and Jürgen Teich. "Run-time Requirement Enforcement for Loop Programs on Processor Arrays." Proceedings of the 16th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), Peking Ed. ACM, IEEE, 2018. 1-11.

BibTeX: 

Zuletzt aktualisiert 2018-04-09 um 13:08