A Journey into DSL Design using Generative Programming: FPGA Mapping of Image Border Handling through Refinement

Beitrag bei einer Tagung
(Konferenzbeitrag)


Details zur Publikation

Autor(en): Özkan MA, Pérard-Gayot A, Membarth R, Slusallek P, Teich J, Hannig F
Verlag: VDE
Jahr der Veröffentlichung: 2018
Tagungsband: Proceedings of the Fifth International Workshop on FPGAs for Software Programmers
ISBN: 978-3-8007-4723-8
Sprache: Englisch


Abstract

Field Programmable Gate Arrays (FPGAs) are continually improving their computing capabilities and energy efficiency.
Yet, programming FPGAs remains a time-consuming task and requires expert knowledge to obtain good performance.
Whereas recent advancements in High-Level Synthesis (HLS) promise to solve this problem, today’s HLS tools need
low-level optimizations such that an application-tailored FPGA implementation for a target algorithm needs to
be described using vendor-specific compiler hints and requires code restructuring. Despite the pursuit of new programming methodologies for many-core, multi-threading, or vector architectures, the FPGA community mostly tries
to improve the design techniques from existing programming languages that are either sequential or developed for
other computing platforms. In this paper, we investigate a state-of-the-art functional language, namely Impala,
that offers explicit control over code refinement. To demonstrate our approach, we examine the description of image border handling for stencil functions and present elegant code descriptions. Besides, we show that the low-level
descriptions can easily be refined to high-level abstractions and serving software developers in the form of either a DSL or a library.


FAU-Autoren / FAU-Herausgeber

Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Özkan, Mehmet Akif
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Autor(en) der externen Einrichtung(en)
Universität des Saarlandes
Universität des Saarlandes (UdS)


Zitierweisen

APA:
Özkan, M.A., Pérard-Gayot, A., Membarth, R., Slusallek, P., Teich, J., & Hannig, F. (2018). A Journey into DSL Design using Generative Programming: FPGA Mapping of Image Border Handling through Refinement. In Proceedings of the Fifth International Workshop on FPGAs for Software Programmers. Dublin, IE: VDE.

MLA:
Özkan, Mehmet Akif, et al. "A Journey into DSL Design using Generative Programming: FPGA Mapping of Image Border Handling through Refinement." Proceedings of the International Workshop on FPGAs for Software Programmers, Dublin VDE, 2018.

BibTeX: 

Zuletzt aktualisiert 2018-01-10 um 17:53